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CMM1530-LC
Advanced Product Information November 2002 (1 of 4) Features Operation as Low as 3.0V 38% Linear Power Added Efficiency +30 dBm Output Power (IS-136 TDMA Mode) +28.5 dBm Output Power (IS-98 CDMA Mode) 32 dB Gain at Operating Output Tested Under Digital Modulation New Low-Cost, Thermally Enhanced, LCC-8 Package PHEMT Material Technology Applications PCS Handsets PCS Base Stations Wireless Local Loop Subscriber Units CDMAone Handsets
1.85 to 1.91 GHz 3.0V, 30 dBm, PCS/PCN LCC-8 Power Amplifier
Functional Block Diagram
Ground Tab Vg2 1 Vg1 2 RF IN 3 Vd1 4 8 Vg3 7 RF OUT/Vd3 6 RF OUT/Vd3 5 Vd2 Ground Tab
Description
The CMM1530-LC is a linear power amplifier intended for use in PCS handsets and wireless local loop subscriber units. The amplifier can be biased to meet the requirements of PCS-1900, IS-136 (TDMA), IS-98 (CDMA) or DCS1800 systems. It is a member of Celeritek's new Triniti DX ProTM family of 3V power amplifier MMICs.
The CMM1530-LC is packaged in a low-cost, space efficient, LCC-8 package that provides excellent electrical stability and low thermal resistance. The part requires minimal external circuitry for bias and matching to reduce space and cost. This device is unconditionally stable under all source and load impedances.
Absolute Maximum Ratings
Parameter Rating Parameter Rating Parameter Rating
Drain Voltage (+Vd) Drain Current (Id) RF Input Power DC Gate Voltage (-Vg)
+5.5 V* 1.8 A 3 dBm* -3.0 V*
Power Dissipation Thermal Resistance Storage Temperature
5W 20C/W -65C to +150C
Operating Temperature Channel Temperature Soldering Temperature
-40C to +90C 150C 260C for 5 Sec.
* Max (+Vd) and (-Vg) under linear operation. Max potential difference across the device at 1dB gain compression point (2Vd + |-Vg|) not to exceed the minimum breakdown voltage (Vbr) of +12V.
Recommended Operating Conditions
Parameter Typ Units Parameter Typ Units
Drain Voltage (+Vd)
3.0 to 4.2
Volts
Operating Temperature (PC Board)
-30 to +80
C
Application Information
The CMM1530-LC is a three stage amplifier that requires a positive and a negative supply voltages for proper operation. It is essential when turning on the device that the negative supply be applied before the positive supply. When turning the device off, the positive supply should be removed before the negative supply is removed. The CMM1530-LC can be operated over a range of supply voltages and bias points. It is important that the maximum power dissipation of the package be observed at all times and that the maximum voltage across the device is not exceeded.
Circuit Design Considerations
Biasing Negative gate voltages are necessary to set the bias currents of the three FET stages in the CMM1530-LC. The first stage gate bias voltage is applied to Vg1 (Pin 2). The second stage gate bias voltage is applied to Vg2 (Pin 1), while the
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third stage FET gate bias is applied to Vg3 (Pin 8). It is desirable to use one or more DACs (digital to analog converters) along with appropriate divider networks, in order to adjust the quiescent currents to within 10 mA of the target values. As an example, for CDMA applications the target quiescent current of the third FET is 85 mA, while those for the second and the first FETs are 45 and 15 mA, respectively. The total quiescent is 135 mA. It is also recommended that the quiescent currents be set in the following sequence: the third stage FET is set first, followed by the second stage FET, followed by the first stage FET. The negative supply voltages control the quiescent currents through each of the FETs and, therefore, control the output power, adjacent channel power ratios, and the currents at the full output power. The positive supply voltages are applied to Pins 4, 5, 6 and 7.
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CMM1530-LC
Electrical Characteristics
Parameter Condition
Advanced Product Information - November 2002
(2 of 4)
Unless otherwise specified, the following specifications are guaranteed at room temperature with drain voltage (+Vd) = 3.5 V in Celeritek test fixture.
Min Typ Max Units
Frequency Range Gain Gain Ripple* Gain Variation Power Output Control Range Power Output Harmonics Noise Power in Receive Band Linearity
Spurious Signal Noise Figure Input Return Loss Output Return Loss Efficiency (Vdd = 3.0 V) Positive Supply Current (Id) Quiescent Current (Iq) Negative Supply Current (-Ig) Negative Supply Voltage (-Vg)
@ Digital power output 1805-1880 MHz & 1850-1910 MHz Over supply voltage Over temperature Vdd = 0 V to +3.5 V Meets IS-136 TDMA mask Meets IS-98 CDMA mask 2nd @ Digital power output, no output trapping, Po=+28.5 dBm 3rd @ Digital power output, no output trapping, Po=+28.5 dBm 30 kHz bandwidth CDMA modulation @ +28.5 dBm Pout, 1.25 MHz offset TDMA modulation @ +30 dBm Pout - Adjacent TDMA modulation @ +30 dBm Pout - Alternate VSWR = 3:1 in-band, VSWR = 10:1 out-of-band
1.85 28
1.91 31 1.5 2 0.03 50 +30.0 +28.5 -30 -40 -94
-45 -26 -45 -80 3.0 10 8 38 35 750 595 130 200 1.1 -0.8
Pout = +30.0 dBm - TDMA Pout = +28.5 dBm - CDMA Pout IS-136 TDMA Pout IS-98 CDMA No RF CDMA mode No RF TDMA mode Includes external resistor divider Into external resistor divider
36 32
-0.5
2.0 -1.4
GHz dB dB dB/V dB/C dB dBm dBm dBc dBc dBm dBc/30KHz dBc dBc dBc dB dB dB % % mA mA mA mA mA V
* Specifications guaranteed over the temperature range of -20C to +80C
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It is very important to provide adequate de-coupling between the RF and DC signals in designing the DC bias circuit. Inadequate by-pass capacitance and inductance around the DC supply lines can compromise the adjacent channel power ratio (ACPR), or reduce power gain and/or create oscillations. The recommend DC by-pass capacitance and low-pass in-line inductance are shown in the evaluation board on Page 4. Matching Circuits Output matching and input matching circuits are required to achieve the RF specifications in this data sheet. The recommend matching circuits are identical to the matching circuits for the evaluation board shown on Page 4. For output power matching, one shunt capacitor along the transmission line connected to Pins 6 and 7 as well as the bond wire inside the package from the output leads to the output FET are used to transform 50 impedance to the load line resistance of the output FET. The placement and the value of the capacitor are important in achieving the performance desired. Matching circuits for the frequencies other than the one shown can be achieved by changing the capacitor value and the placement position of the capacitor. The device can be designed to work from UHF to around 3 GHz. Supply Ramping To obtain power ramping, gate supply control is recommend. Drain supply voltage ramping can also be used.
Modulation When biased as specified, the CMM1530-LC will achieve the required adjacent channel response for the digital PCS system specified. Celeritek tests each product under digital modulation to ensure correlation to customer applications. Thermal 1. The copper pad on the backside of the CMM1530-LC must be soldered to the ground plane. 2. All 8 leads of the package must be soldered to the appropriate electrical connection.
Typical Performance
Wideband Gain & Return Loss vs Frequency @ 3.5 V, +25C
Gain, dB 35 30 25 20
Input Return Loss Gain
-20 -30 -40
0.5
1.0
1.5 2.0 Frequency, GHz
2.5
3.0
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Return Loss, dB
Output Return Loss
0 -10
CMM1530-LC
Advanced Product Information - November 2002 Typical Performance (Continued)
Gain & IS-136 TDMA Output Power vs Frequency Over Voltage @ +25C Power Out, dBm
32 3.3 V 30 3.0 V 2.7 V
(3 of 4)
Korean CDMA Spectral Mask (Vdd=3.5V, 1,752 MHz, Po=+28.5 dBm)
1.85 Frequency, GHz
27 1.91
IS-136 TDMA Spectral Mask (Vdd=3.5V, 1,880 MHz, Po=+30 dBm)
Gain, dB
3.3 V 3.0 V 2.7 V
29
IS-98 CDMA Spectral Mask (Vdd=3.5V, 1,880 MHz, Po=+28.5 dBm)
Id & IS-136 TDMA ACPR vs Power Output (3.5V, 1.91 GHz)
1000 800
Id & IS-98 CDMA ACPR vs Power Output (3.5V, 1.91 GHz) Id, mA
Id, mA
Id Adjacent Chanel Power Ratio, dBc
200 -20 -40 -60 21.75 24.5 27.25 30 Power Output, dBm (30 kHz BW) Adjacent channel power (worst case, Fc 30 kHz) Alternate channel power (worst case, Fc 60 kHz)
100
-45 -50 -55 7.125 14.5 21.625 28.5 Power Output, dBm (1.25 MHz BW) Adjacent channel power (worst case 1.25 MHz)
19
0
Power Output, dBm
TDMA Power Output and Efficiency vs Input Power (3.0V, 1.91 GHz) Power Output, dBm
35 25 15 52.5
CDMA Power Output, 2nd and 3rd Harmonics vs Input Power (3.5V, 1.91 GHz)
35 25 15 5 -30 -45 -60 -2.5
Efficiency, %
35.0 17.5 0 -1
3rd
-13
-10
-4 -7 Input Output, dBm
-26.5
-20.5
-8.5 -14.5 Input Output, dBm
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Santa Clara, California 95054
Phone: (408) 986-5060
Fax: (408) 986-5095
Harmonics, dBc
2nd
Adjacent Chanel Power Ratio, dBc/30 kHz
600
400
CMM1530-LC
Recommended Matching Topology
65 Vgg 1.5 K 130 C1 10 F C5 100 pF C3 100 pF 1 2 RF IN C8 5600 pF 3 50 L1 47 nH C14 0.01 F
Advanced Product Information - November 2002
(4 of 4)
Note: This schematic represents the topology of the matching circuit recommended by Celeritek. 1.5 K C13 0.01 F C4 100 pF 40 30 @ 1.88 GHz C15 3.3 pF C6 100 pF C7 100 pF RF OUT C16 50 0.7 pF
Evaluation Board Schematic Board substrate: ER = 4.60 Thickness = 0.031 in.
8 7 6
uu uu
uu uu
4 5 CMM1530-LC L2 47 nH C10 5600 pF
uu uu
15nH or 100 90 @ 1.88 GHz R5 51 K
Vcc TX
C12 0.01 F
C9 5600 pF
C11 0.01 F
C2 10 F
Physical Dimensions
Ordering Information
The CMM1530-LC is available in a surface mount LCC-8 package and devices are available in tube or tape and reel. Part Number for Ordering Package CMM1530-LC-00S0 LCC-8 CDMA surface mount power package in tube CMM1530-LC-00T0 LCC-8 TDMA surface mount power package in tube CMM1530-LC-00ST LCC-8 CDMA surface mount power package in tape and reel CMM1530-LC-00TT LCC-8 TDMA surface mount power package in tape and reel PB-CMM1530-LC-00S0 Evaluation Board with SMA connectors for CMM1530-LC-00S0 tested CDMA PB-CMM1530-LC-00T0 Evaluation Board with SMA connectors for CMM1530-LC-00T0 tested TDMA
Celeritek reserves the right to make changes without further notice to any products herein. Celeritek makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Celeritek assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Celeritek does not convey any license under its patent rights nor the rights of others. Celeritek products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Celeritek product could create a situation where personal injury or death may occur. Should Buyer purchase or use Celeritek products for any such unintended or unauthorized application, Buyer shall indemnify and hold Celeritek and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Celeritek was negligent regarding the design or manufacture of the part. Celeritek is a registered trademark of Celeritek, Inc. Celeritek, Inc. is an Equal Opportunity/Affirmative Action Employer.
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